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asahi kasei [ak5385b] ms0406-e-00 2005/08 - 1 - general description the ak5385b is a 24bit, 192khz sampling 2ch a/d converter for high-end audio system. the modulator in the ak5385b uses the enhanced dual bit architecture and the ak5385b realizes high accuracy and low cost. the ak5385b performs 114db dynamic range, so the device is suitable for av-amp, av recorder and musical instruments. the ak5385b is available in 28pin vsop and sop package, utilizing less board space. features ? sampling rate: 8khz ~ 216khz ? full differential inputs ? s/(n+d): 103db ? dr: 114db ? s/n: 114db ? high performance linear ph ase digital anti-alias filter ? passband: 0~21.768khz (@fs=48khz) ? ripple: 0.005db ? stopband: 100db ? digital hpf ? power supply: 5v 5%(analog), 3.0 ~ 5.25v(digital) ? power dissipation: 183mw (@fs=48khz) ? package: 28pin sop / 28pin vsop ? ak5383/ak5393/ak5394a semi-pin compatible test decimation filter delta-sigma modulator decimation filter hpf hpf audio i/f controller dvdd avdd dvss avss vrefr vrefl lin+ lin- delta-sigma modulator rin+ rin- dif pdn lrck bick mclk sdto hpfe m/s dfs1 dfs0 cks1 cks0 vcom bvss ovf block diagram 24bit 192khz ? adc ak5385b
asahi kasei [ak5385b] ms0406-e-00 2005/08 - 2 - ? ordering guide ak5385bvs ?10 ~ +70 c 28pin sop (1.27mm pitch) AK5385BVF ?40 ~ +85 c 28pin vsop (0.65mm pitch) akd5385b evaluation board for ak5385b ? pin layout vcom lin+ dvdd dvss vrefl avss lin- cks0 pdn dif m/s lrck bick ovf top view 8 7 6 5 4 3 2 1 21 22 23 24 25 26 27 28 test rin+ avss avdd rin- avss vrefr 9 10 11 12 13 14 18 19 20 hpfe 15 16 17 sdto cks1 mclk dfs1 bvss dfs0
asahi kasei [ak5385b] ms0406-e-00 2005/08 - 3 - ? compatibility with ak5383/ak5394a ak5385b ak5383 ak5394a pin 1 vrefl vrefl vrefl+ pin 2 avss gndl vrefl ? pin 3 vcom vcoml vcoml pin 6 cks0 zcal zcal pin 9 ovf cal cal pin 11 dif smode2 smode2 pin 12 m/s smode1 smode1 pin 16 cks1 fsync fsync pin 18 dfs0 dfs dfs0 pin 20 dfs1 test dfs1 pin 26 test vcomr vcomr pin 27 avss gndr vrefr ? pin 28 vrefr vrefr vrefr+ fs 8khz 216khz 1khz 108khz 1khz 216khz mclk at 48khz 256/384/512fs 256fs 256fs mclk at 96khz 256fs 128fs 128fs mclk at 192khz 128fs not available 64fs dr, s/n 114db 110db 123db input voltage 2.9vpp 2.45vpp 2.4vpp offset calibration not available available available
asahi kasei [ak5385b] ms0406-e-00 2005/08 - 4 - ? compare pcb layout example between ak5385b and ak5383 3.0 ~ 5.25v digital vrefl gndl 1 2 3 4 5 6 7 8 9 10 11 12 13 14 vcoml ainl+ ainl- zcal vd dgnd cal rstn smode2 smode1 lrck sclk 28 27 26 25 24 23 22 21 20 19 18 17 16 15 vrefr gndr vcomr ainr+ ainr- va agnd bgnd test hpfe dfs mclk fsync sdata 0.1 10 0.22 0.1 10 0.1 10 5v analog analog ground 0.1 10 0.22 3.0 ~ 5.25v digital vrefl avss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 vcom lin+ lin- cks0 dvdd dvss ovf pdn dif m/s lrck bick 28 27 26 25 24 23 22 21 20 19 18 17 16 15 vrefr avss test rin+ rin- avdd avss bvss dfs1 hpfe dfs0 mclk cks1 sdto 10 0.22 0.1 10 0.1 10 5v analog 10 ak5385b ak5383 0.1 analog ground 0.1 pin # ak5383 ak5385b vrefl vrefl 1 lch voltage reference output pin, 3.75v normally, connected to gndl with a 10 f electrolytic capacitor and a 0.1 f ceramic capacitor. lch voltage reference input pin, avdd normally, connected to avss with a 10 f electrolytic capacitor and a 0.1 f ceramic capacitor. zcal cks0 6 zero calibration control pin this pin controls the calibration reference signal. master clock select 0 pin (internal pull-down pin, typ. 100k ? ) cal ovf 9 calibration active signal pin analog input overflow detect pin smode2 dif 11 serial interface mode select pin audio interface format pin smode1 m/s 12 serial interface mode select pin master / slave mode pin fsync cks1 16 frame synchronization signal pin master clock select 1 pin (internal pull-down pin, typ.100k ? ) dfs dfs0 18 double speed sampling mode pin sampling speed select 0 pin test dfs1 20 test pin (internal pull-down pin) sampling speed select 1 pin vcomr test 26 rch common voltage pin, 2.75v test pin (internal pull-down pin, typ. 100k ? ) vrefr vrefr 28 rch voltage reference output pin, 3.75v normally, connected to gndl with a 10 f electrolytic capacitor and a 0.1 f ceramic capacitor. rch voltage reference input pin, avdd normally, connected to avss with a 10 f electrolytic capacitor and a 0.1 f ceramic capacitor.
asahi kasei [ak5385b] ms0406-e-00 2005/08 - 5 - ? compare pcb layout example between ak5385b and ak5394a 3.0 ~ 5.25v digital vrefl+ vrefl- 1 2 3 4 5 6 7 8 9 10 11 12 13 14 vcoml ainl+ ainl- zcal vd dgnd cal rstn smode2 smode1 lrck sclk 28 27 26 25 24 23 22 21 20 19 18 17 16 15 vrefr+ vrefr- vcomr ainr+ ainr- va agnd bgnd dfs1 hpfe dfs0 mclk fsync sdata 0.1 10 0.22 0.1 10 0.1 10 5v analog analog ground 0.1 10 0.22 ak5394a 10 10 3.0 ~ 5.25v digital vrefl avss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 vcom lin+ lin- cks0 dvdd dvss ovf pdn dif m/s lrck bick 28 27 26 25 24 23 22 21 20 19 18 17 16 15 vrefr avss test rin+ rin- avdd avss bvss dfs1 hpfe dfs0 mclk cks1 sdto 0.1 10 0.22 0.1 10 0.1 10 5v analog 0.1 10 ak5385b (short) (short) analog ground pin # ak5394a ak5385b vrefl+ vrefl 1 lch positive voltage reference output pin, 3.75v normally connected to agnd with a large electrolytic capacitor and connected to vrefl ? with a 0.22 f ceramic capacitor. lch voltage reference input pin, avdd normally, connected to avss with a 10 f electrolytic capacitor and a 0.1 f ceramic capacitor. vrefl ? avss 2 lch negative voltage reference output pin, 1.25v normally connected to agnd with a large electrolytic capacitor and connected to vrefl+ with a 0.22 f ceramic capacitor. analog ground pin zcal cks0 6 zero calibration control pin this pin controls the calibration reference signal. master clock select 0 pin (internal pull-down pin, typ. 100k ? ) cal ovf 9 calibration active signal pin analog input overflow detect pin smode2 dif 11 serial interface mode select pin audio interface format pin smode1 m/s 12 serial interface mode select pin master / slave mode pin fsync cks1 16 frame synchronization signal pin master clock select 1 pin (internal pull-down pin, typ. 100k ? ) vrefr ? avss 27 rch negative voltage reference output pin, 1.25v normally connected to agnd with a large electrolytic capacitor and connected to vrefr+ with a 0.22 f ceramic capacitor. analog ground pin vcomr test 26 rch common voltage pin, 2.75v test pin (internal pull-down pin, typ. 100k ? ) vrefr+ vrefr 28 rch positive reference output voltage, 3.75v normally connected to agnd with a large electrolytic capacitor and connected to vrefr ? with a 0.22 f ceramic capacitor. rch voltage reference input pin, avdd normally, connected to avss with a 10 f electrolytic capacitor and a 0.1 f ceramic capacitor.
asahi kasei [ak5385b] ms0406-e-00 2005/08 - 6 - pin / function no. pin name i/o function 1 vrefl i lch voltage reference input pin, avdd normally, connected to avss with a 10 f electrolytic capacitor and a 0.1 f ceramic capacitor. 2 avss - analog ground pin 3 vcom o common voltage output pin, avdd/2 4 lin+ i lch analog positive input pin 5 lin ? i lch analog negative input pin 6 cks0 i master clock select 0 pin (internal pull-down pin, typ. 100k ? ) 7 dvdd - digital power supply pin, 3.0 5.25v 8 dvss - digital ground pin 9 ovf o analog input overflow detect pin this pin goes to ?h? if analog input overflows. 10 pdn i power down mode pin ?h?: power up, ?l?: power down 11 dif i audio interface format pin ?h? : 24bit i 2 s compatible, ?l? : 24bit msb justified 12 m/s i master / slave mode pin ?h? : master mode, ?l? : slave mode 13 lrck i/o output channel clock pin ?l? output in master mode at power-down mode. 14 bick i/o audio serial data clock pin ?l? output in master mode at power-down mode. 15 sdto o audio serial data output pin ?l? output at power-down mode. 16 cks1 i master clock select 1 pin (internal pull-down pin, typ. 100k ? ) 17 mclk i master clock input pin 18 dfs0 i sampling speed select 0 pin 19 hpfe i high pass filter enable pin ?h? : enable, ?l? : disable 20 dfs1 i sampling speed select 1 pin 21 bvss - substrate ground pin 22 avss - analog ground pin 23 avdd - analog power supply pin, 4.75 5.25v 24 rin ? i rch analog negative input pin 25 rin+ i rch analog positive input pin 26 test i test pin (internal pull-down pin, typ. 100k ? ) 27 avss - analog ground pin 28 vrefr i rch voltage reference input pin, avdd normally, connected to avss with a 10 f electrolytic capacitor and a 0.1 f ceramic capacitor. note: all digital input pins except pull-down pins should not be left floating.
asahi kasei [ak5385b] ms0406-e-00 2005/08 - 7 - ? handling of unused pin the unused i/o pins should be processed appropriately as below. classification pin name setting lin+, lin ? these pins should be connected to avss. rin+, rin ? these pins should be connected to avss. analog vrefl, vrefr these pins should be connected to avdd. ovf this pin should be open. digital test this pin should be connected to dvss. absolute maximum ratings (avss, bvss, dvss=0v; note 1) parameter symbol min max units power supplies: analog digital |bvss ? dvss| (note 2) avdd dvdd ? gnd ? 0.3 ? 0.3 - 6.0 6.0 0.3 v v v input current, any pin except supplies iin - 10 ma analog input voltage (lin+/?, rin+/?, vrefl/r pins) vina ? 0.3 avdd+0.3 v digital input voltage (all digital input pins) vind ? 0.3 dvdd+0.3 v ambient temperature (power applied) 28sop package 28vsop package ta ta ? 10 ? 40 70 85 c c storage temperature tstg ? 65 150 c note 1. all voltages with respect to ground. note 2. avss bvss, and dvss must be connected to the same analog ground plane. warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. recommended operating conditions (avss, bvss, dvss=0v; note 1) parameter symbol min typ max units power supplies (note 3) analog digital avdd dvdd 4.75 3.0 5.0 3.3 5.25 avdd v v voltage reference (vrefl/r pins) vref 3.0 - avdd v note 1. all voltages with respect to ground. note 3. the power up sequence between avdd and dvdd is not critical. warning: akm assumes no responsibility for the usage beyond the conditions in this datasheet.
asahi kasei [ak5385b] ms0406-e-00 2005/08 - 8 - analog characteristics (ta=25 c; avdd=5.0v, dvdd=3.3v; avss=bvss=dvss=0v; vrefl=vrefr=avdd; fs=48khz, 96khz, 192khz; bick=64fs; signal frequency=1khz; 24bit data; measurement frequency=20hz 20khz at fs=48khz, 40hz 40khz at fs=96khz, 40hz 40khz at fs=192khz; unless otherwise specified) parameter min typ max units analog input characteristics: resolution 24 bits input voltage (note 4) 2.7 2.9 3.1 vpp fs=48khz bw=20khz ? 1dbfs (note 5) ? 1dbfs ? 20dbfs ? 60dbfs - 92 - - 103 100 91 51 db db db db fs=96khz bw=40khz ? 1dbfs ? 20dbfs ? 60dbfs 90 - - 98 86 46 db db db s/(n+d) fs=192khz bw=40khz ? 1dbfs ? 20dbfs ? 60dbfs - - - 98 86 46 db db db dynamic range ( ? 60dbfs with a-weighted) 107 114 db s/n (a-weighted) 107 114 db input resistance 9 13 k ? interchannel isolation 100 120 db interchannel gain mismatch 0.1 0.5 db power supply rejection (note 6) 50 - db power supplies power supply current normal operation (pdn pin = ?h?) avdd dvdd (fs=48khz) dvdd (fs=96khz) dvdd (fs=192khz) power down mode (pdn pin = ?l?) (note 7) avdd+dvdd 30 10 17 20 10 45 15 25 30 100 ma ma ma ma a note 4. this value is (lin+) ? (lin ? ) and (rin+) ? (rin ? ). input voltage is proportional to vref voltage. vin = 0.58 x vref (vpp). note 5. 100 f capacitors are connected between the vrefl/r pins and avss. note 6. psr is applied to avdd and dvdd with 1khz, 20mvpp. the vrefl and vrefr pins held a constant voltage. note 7. all digital input pins are held dvdd or dvss.
asahi kasei [ak5385b] ms0406-e-00 2005/08 - 9 - filter characteristics (fs=48khz) (ta=25 c; avdd=4.75 5.25v; dvdd=3.0 5.25v; dfs1 = ?l?, dfs0 = ?l?) parameter symbol min typ max units adc digital filter (decimation lpf): passband (note 8) ? 0.005db ? 0.02db ? 0.06db ? 6.0db pb 0 - - - 22.038 22.2 24.0 21.5 - - - khz khz khz khz stopband sb 26.5 khz passband ripple pr 0.005 db stopband attenuation sa 100 db group delay (note 9) gd 43.2 1/fs group delay distortion ? gd 0 s adc digital filter (hpf): frequency response (note 8) ? 3db ? 0.1db fr 1.0 6.5 hz hz filter characteristics (fs=96khz) (ta=25 c; avdd=4.75 5.25v; dvdd=3.0 5.25v; dfs1 = ?l?, dfs0 = ?h?) parameter symbol min typ max units adc digital filter (decimation lpf): passband (note 8) ? 0.005db ? 0.02db ? 0.06db ? 6.0db pb 0 - - - 44.081 44.5 48.0 43.0 - - - khz khz khz khz stopband sb 53.0 khz passband ripple pr 0.005 db stopband attenuation sa 100 db group delay (note 9) gd 43.1 1/fs group delay distortion ? gd 0 s adc digital filter (hpf): frequency response (note 8) ? 3db ? 0.1db fr 2.0 13.0 hz hz note 8. the passband and stopband frequencies scale with fs . the reference frequency of these responses is 1khz. note 9. the calculated delay time induced by digital filtering. this time is from the input of an analog signal to the setting of 24bit data both channels to the adc output register for adc.
asahi kasei [ak5385b] ms0406-e-00 2005/08 - 10 - filter characteristics (fs=192khz) (ta=25 c; avdd=4.75 5.25v; dvdd=3.0 5.25v; dfs1 = ?h?, dfs0 = ?l?) parameter symbol min typ max units adc digital filter (decimation lpf): passband (note 8) ? 0.005db ? 0.02db ? 0.06db ? 6.0db pb 0 - - - 88.183 89.0 96.0 86.0 - - - khz khz khz khz stopband sb 106.0 khz passband ripple pr 0.005 db stopband attenuation sa 100 db group delay (note 9) gd 38.2 1/fs group delay distortion ? gd 0 s adc digital filter (hpf): frequency response (note 8) ? 3db ? 0.1db fr 4.0 26.0 hz hz note 8. the passband and stopband frequencies scale with fs . the reference frequency of these responses is 1khz. note 9. the calculated delay time induced by digital filtering. this time is from the input of an analog signal to the setting of 24bit data both channels to the adc output register for adc. dc characteristics (ta=25 c; avdd=4.75 5.25v; dvdd=3.0 5.25v) parameter symbol min typ max units high-level input voltage low-level input voltage vih vil 70%dvdd - - - - 30%dvdd v v high-level output voltage (iout= ? 400 a) low-level output voltage (iout=400 a) voh vol dvdd ? 0.4 - - - - 0.4 v v input leakage current (note 10) iin - - 10 a note 10. cks1, cks0 and test pins are internally connected to a pull-down resistor. (typ. 100k ? )
asahi kasei [ak5385b] ms0406-e-00 2005/08 - 11 - switching characteristics (ta=25 c; avdd=4.75 5.25v; dvdd=3.0 5.25v; c l =20pf) parameter symbol min typ max units master clock timing frequency pulse width low pulse width high fclk tclkl tclkh 2.048 14.5 14.5 27.648 mhz ns ns lrck frequency normal speed mode double speed mode quad speed mode fsn fsd fsq 8 54 108 54 108 216 khz khz khz duty cycle slave mode master mode 45 50 55 % % audio interface timing slave mode bick period normal speed mode double speed mode quad speed mode bick pulse width low pulse width high lrck edge to bick ? ? (note 11) bick ? ? to lrck edge (note 11) lrck to sdto (msb) (except i 2 s mode) bick ? ? to sdto tbck tbck tbck tbckl tbckh tlrb tblr tlrs tbsd 1/128fsn 1/64fsd 1/64fsq 33 33 20 20 20 20 ns ns ns ns ns ns ns ns ns master mode bick frequency bick duty bick ? ? to lrck bick ? ? to sdto fbck dbck tmblr tbsd ? 20 ? 20 64fs 50 20 20 hz % ns ns reset timing pdn pulse width (note 12) pdn ? ? to sdto valid (note 13) tpd tpdv 150 516 ns 1/fs note 11. bick rising edge must not occur at the same time as lrck edge. note 12. the ak5385b can be reset by bringing the pdn pin = ?l?. note 13. this cycle is the number of lrck rising edges from the pdn pin = ?h?. this value is in master mode this value is longer 1/fs in slave mode than master mode.
asahi kasei [ak5385b] ms0406-e-00 2005/08 - 12 - ? timing diagram 1/fclk mclk tclkh tclkl vih vil 1/fs lrck vih vil tbck bick tbckh tbckl vih vil clock timing lrck vih vil tblr bick vih vil tlrs sdto 50%dvdd tlrb tbsd audio interface timing (slave mode)
asahi kasei [ak5385b] ms0406-e-00 2005/08 - 13 - lrck bick 50%dvdd sdto 50%dvdd tbsd tmblr dbck 50%dvdd audio interface timing (master mode) tpd pdn vil pdn vih vil tpdv sdto 50%dvdd power down & reset timing
asahi kasei [ak5385b] ms0406-e-00 2005/08 - 14 - operation overview ? system clock mclk (256fs/384fs/512fs), bick (48fs ) and lrck (fs) clocks are required in slave mode. the lrck clock input must be synchronized with mclk, however the phase is not critical. table 1 shows the relationship of typical sampling frequency and the system clock frequency. mclk frequency is selected by cks1-0 pins as shown in table 2 and lrck frequency is selected by dfs1-0 pins as shown in table 3. as the ak5385b includes the phase detect circuit for lrck, the ak5385b is reset automatically when the synchronization is out of phase by changing the clock frequencies. all external clocks (mclk, bick and lrck) must be pres ent unless pdn pin = ?l?. if these clocks are not provided, the ak5385b may draw excess current due to its use of internal dynamically refreshed logic. if the external clocks are not present, place the ak5385b in power-down mode (pdn pin = ?l?). in master mode, the master clock (mclk) must be provided unless pdn pin = ?l?. mclk fs 128fs 256fs 384fs 512fs 32khz n/a 8.192mhz 12.288mhz 16.384mhz 44.1khz n/a 11.2896mhz 16.9344mhz 22.5792mhz 48khz n/a 12.288mhz 18.432mhz 24.576mhz 96khz n/a 24.576mhz n/a n/a 192khz 24.576mhz n/a n/a n/a table 1. system clock example cks1 pin cks0 pin mclk frequency l l 256fs l h 128fs h l 512fs h h 384fs table 2. mclk frequency dfs1 pin dfs0 pin lrck frequency l l 8khz fs 54khz l h 54khz < fs 108khz h l 108khz < fs 216khz h h n/a table 3. sampling speed when changing mclk frequency in master/slave mode, the ak5385b should reset by pdn pin = ?l?. (ex. 12.288mhz(@fs=48khz) to 24.576mhz(@fs=96kh z) at cks1 pin = cks0 pin = ?l?. if the cks1-0 and dfs1-0 pins are changed with same mclk frequency in master/slave mode (ex. mclk is fixed to 24.576mhz and fs is changed from 48khz (cks1 pin = ?l?, cks0 pin = ?l?) to 96khz (cks1 pin = ?l?, cks0 pin = ?h?)), no reset by pdn pin = ?l? is required.
asahi kasei [ak5385b] ms0406-e-00 2005/08 - 15 - ? audio interface format two kinds of data formats can be chosen with the dif pin (tab le 4). in both modes, the serial data is in msb first, 2?s complement format. the sdto is clocked out on the falling edge of bick. the audio interface supports both master and slave modes. in master mode, bick and lrck are output with the bick frequency fixed to 64fs and the lrck frequency fixed to 1fs. mode dif pin sdto lrck bick figure 0 l 24bit, msb justified h/l 48fs figure 1 1 h 24bit, i 2 s compatible l/h 48fs figure 2 table 4. audio interface format lrck bick(64fs) sdto(o) 0 23 22 1 2 4 0 20 21 24 31 0 12 23 22 0 1 0 23 22 20 21 31 23:msb, 0:lsb lch data rch data 24 321 22 23 23 1 2 3 4 figure 1. mode 0 timing lrck bick(64fs) sdto(o) 0 23 22 1 2 4 0 25 21 24 0 12 23 22 0 1 0 22 25 21 24 321 22 23 23 1 2 3 4 3 23:msb, 0:lsb lch data rch data figure 2. mode 1 timing ? master mode and slave mode the m/s pin selects either master or slave modes. m/s pin = ?h? selects master mode and ?l? selects slave mode. the ak5385b outputs bick and lrck in master mode. in slave mode, provide mclk, bick and lrck. m/s pin mode bick, lrck l slave mode bick = input lrck = input h master mode bick = output lrck = output table 5. master mode/slave mode
asahi kasei [ak5385b] ms0406-e-00 2005/08 - 16 - ? digital high pass filter the adc has a digital high pass filter for dc offset ca ncellation. the cut-off frequency of the hpf is 1.0hz (@fs=48khz) and scales with sampling rate (fs). hpf is controlled by hpfe pin. if hpf setting (on/off) is changed at operating, click noise occurs by changing dc offset. it is recommended that hpf setting is changed at pdn pin = ?l?. ? overflow detection the ak5385b has overflow detect function for analog input. ovf pin goes to ?h? if lch or rch overflows (more than ? 0.3dbfs). ovf output for overflowed analog input has th e same group delay as adc (gd=43.2/fs=0.9ms@fs=48khz). ovf is ?l? for 516/fs (=10.75ms@fs=48khz) after pdn pin = ? ?, and then overflow detection is enabled. ? power down and reset the ak5385b is placed in the power-down mode by bringing pdn pin ?l? and the digital filter is also reset at the same time. this reset should always be done after power-up. in the power-down mode, the vcom is agnd level. an analog initialization cycle starts after exiting the power-down mode . therefore, the output data sdto becomes available after 516 cycles of lrck clock in master mode (517 cycles in slave mode). during initialization, the adc digital data outputs of both channels are forced to ?0?. the adc outputs settle in the data corresponding to the input signals after the end of initialization (settling approximately takes th e group delay time). the ak5385b should be reset once by bringing pdn pin ?l? af ter power-up. the internal timing starts clocking by the rising edge (falling edge at mode 1) of lrck after exiting from reset and power down state by mclk. normal operation internal state pdn power-down initialize normal operation (1) idle noise gd gd ?0?data a /d in (analog) a /d out (digital) clock in mclk,lrck,sclk (2) (3) (4) ?0?data idle noise notes: (1) 517/fs in slave mode and 516/fs in master mode. (2) digital output corresponding to analog input has the group delay (gd). (3) a/d output is ?0? data at the power-down state. (4) when the external clocks (mclk, sclk, lrck) are stopped, the ak5385b should be in the power-down state. figure 3. power-down/up sequence example
asahi kasei [ak5385b] ms0406-e-00 2005/08 - 17 - system design figure 4 shows the system connection diagram. an evaluation board is available which demonstrates application circuits, the optimum layout, power supply arrangements and measurement results. 0.1 10 0.1 10 vrefl 1 2 3 4 5 6 7 8 9 10 11 avss vcom lin+ lin- cks0 dvdd dvss ovf pdn dif ak5385b dsp and up 28 27 26 vrefr avss test digital supply 3.0 ~ 5.25v 12 m/s 13 lrck 14 bick reset 25 24 rin+ rin- 23 22 avdd avss 21 20 bvss dfs1 19 18 hpfe dfs0 17 16 mclk cks1 15 sdto analog supply 4.75 ~ 5.25v 0.1 10 0.22 0.1 10 note: - avss, bvss and dvss of the ak5385b should be distributed separately from the ground of external digital devices (mpu, dsp etc.). - all input pins except pull-down (cks0, cks1 and test pin) pin should not be left floating. figure 4. typical connection diagram analog ground digital ground system controller 1 2 3 4 5 6 7 8 9 10 11 12 28 27 26 25 24 23 22 21 20 19 18 17 14 16 15 vrefl avss vcom lin+ lin- cks0 dvdd dvss ovf dif m/s vrefr a vss test rin+ rin- avdd a vss bvss dfs1 hpfe dfs0 mclk ak5385b lrck bick cks1 sdto pdn 13 figure 5. ground layout note: - avss bvss, and dvss must be connected to the same analog ground plane.
asahi kasei [ak5385b] ms0406-e-00 2005/08 - 18 - 1. grounding and power supply decoupling the ak5385b requires careful attention to power supply and grounding arrangements. alternatively if avdd and dvdd are supplied separately, the power up sequence is not critical. avss, bvss and dvss of the ak5385b must be connected to analog ground plane. system analog ground and digital ground should be connected together near to where the supplies are brought onto the printed circuit board. de coupling capacitors should be as near to the ak5385b as possible, with the small value ceramic capacitor being the nearest. 2. voltage reference inputs the reference voltage for a/d converter is supplied from vrefl/r pins at avss reference. avss pin is connected to analog ground and an electrolytic capacitor over 10 f parallel with a 0.1 f ceramic capacitor between the vrefl/r pins and the avss pin eliminate the effects of high frequency noise. especially, a ceramic capacitor should be as near to the pins as possible. and all digital signals, especially clocks, should be kept away from the vrefl/r pins in order to avoid unwanted coupling into the ak5385b. no load current may be taken from the vrefl/r pins. vcom is a signal ground of this chip. an electrolytic capacitor 0.22f attached to vcom pin eliminates the effects of high frequency noise. no load current may be drawn from the vcom pin. all signals, especially clocks, should be kept away from the vcom pin in order to avoid unwanted coupling into the ak5385b. 3. analog inputs analog signal is differentially input into the modulator via the lin+ (rin+) and the lin ? (rin ? ) pins. the input voltage is the difference between the lin+ (rin+) and lin ? (rin ? ) pins. the full scale of each pin is nominally 2.9vpp(typ). the ak5385b can accept input voltages from avss to avdd. the adc output data format is 2?s complement. the internal hpf removes the dc offset. the ak5385b samples the analog inputs at 128fs (6.144mhz@fs=48khz, normal speed mode). the digital filter rejects noise above the stop band except for multiples of 128fs. the ak5385b includes an anti-aliasing filter (rc filter) to attenuate a noise around 128fs. the ak5385b accepts +5v supply voltage. any voltage which exceeds the upper limit of avdd+0.3v and lower limit of avss ? 0.3v and any current beyond 10ma for the analog input pins (lin+/ ? , rin+/ ? ) should be avoided. excessive currents to the input pins may damage the device. hence input pins must be protected from signals at or beyond these limits. use caution specially in case of using 15v in other analog circuits.
asahi kasei [ak5385b] ms0406-e-00 2005/08 - 19 - 4. external analog circuit examples figure 6 shows an input buffer circuit example 1. this is a full-differential input buffer circuit with an inverted-amp (gain: ? 10db). the capacitor of 10nf between lin+/ ? (rin+/ ? ) decreases the clock feed through noise of modulator, and composes a 1st order lpf (fc=360khz) with 22 ? resistor before the capacitor. this circuit also has a 1st order lpf (fc=370khz) composed of op-amp. the evaluation board should be referred about the detail. 4 5 lin+ lin- ak5385b analog in 4.7k 4.7k vp+ vp- njm5532 47 3k 470p 910 22 47 3k 470p 910 22 bias 10n 9.56vpp 2.9vpp 2.9vpp bias 10 0.1 bias 10k 10k va va = 5v vp+ = 15v vp- = -15v figure 6.input buffer example figure 7 shows an input buffer circuit example 2. (1 st order hpf: fc=0.66hz, table 6; 1 st order lpf: fc=590khz, gain= ? 14db, table 7). the analog signal is able to input through xlr or bnc connectors. (short jp1 and jp2 for bnc input, open jp1 and jp2 for xlr input). the input level of this circuit is +/ ? 14.7vpp. bnc njm5534 4 5 lin+ lin- ak5385b 4.7k 4.7k jp1 jp2 91 91 1.5n 2.9vpp njm5534 njm5534 1k 22 1k 22 10k 10k 4.7k 4.7k va 10 0.1 vin- vin+ xlr 100 2.9vpp 14.7vpp 14.7vpp bias figure 7.input buffer example fin 1hz 10hz frequency response ? 1.56db ? 0.02db table 6. frequency response of hpf fin 20khz 40khz 6.144mhz frequency response ? 0.005db ? 0.02db ? 15.6db table 7. frequency response of lpf
asahi kasei [ak5385b] ms0406-e-00 2005/08 - 20 - 5. measurement example figure 8 shows the s/(n+d) vs. vref capacitor that is connected between vrefl/r pins and avss pin with the 0.1 f capacitor in parallel. x-axis is the capacity for vref; y-axis is s/(n+d). [measurement condition] - avdd = 5.0v, dvdd = 3.3v; avss = bvss = dvss = 0v - fs = 48khz - measurement bandwidth = 10hz 20khz - ta = 25 c - using audio precision system two cascade s/(n+d) vs. vref cap 100.0 101.0 102.0 103.0 104.0 105.0 106.0 0 50 100 150 200 250 vref cap [uf] s/(n+d) [db] lch rch figure 8. s/(n+d) vs. vref cap 6. synchronization of multiple devices in system where multiple adcs are required, care must be taken to achieve simultaneous sampling. to ensure synchronous sampling, the mclk and lrck must be the same for all of the ak5385bs in the system. the all ak5385bs should be reset at the same timing with preventing the reset signal for ak5385b from overlapping on the edge of mclk, so that all ak5385bs begin sampling on the same clock edge.
asahi kasei [ak5385b] ms0406-e-00 2005/08 - 21 - package (AK5385BVF) 0.1 0.1 0-10 detail a seating plane note: dimension "*" does not include mold flash. | 0.10 0.15-0.05 0.22 0.1 0.65 *9.8 0.2 1.25 0.2 a 1 14 15 28 28pin vsop (unit: mm) *5.6 0.2 7.6 0.2 0.5 0.2 +0.1 0.675 ? material & lead finish package molding compound: epoxy lead frame material: cu lead frame surface treatment: solder (pb free) plate
asahi kasei [ak5385b] ms0406-e-00 2005/08 - 22 - package (ak5385bvs) 0-10 0.10 0.15-0.05 1.095typ 18.7 0.3 28pin sop (unit: mm) 7.5 0.2 0.75 0.2 +0.1 10.4 0.3 2.2 0.1 1.27 0.12 m +0.1 0.1-0.05 0.4 0.1 ? material & lead finish package molding compound: epoxy lead frame material: cu lead frame surface treatment: solder (pb free) plate
asahi kasei [ak5385b] ms0406-e-00 2005/08 - 23 - marking (AK5385BVF) akm a k5385bvf xxxbyyyyc xxxbyyyyc date code identifier xxxb : lot number (x : digit number, b : alpha character) yyyyc : assembly date (y : digit number, c : alpha character)
asahi kasei [ak5385b] ms0406-e-00 2005/08 - 24 - marking (ak5385bvs) akm a k5385bvs xxxbyyyyc xxxbyyyyc date code identifier xxxb : lot number (x : digit number, b : alpha character) yyyyc : assembly date (y : digit number, c : alpha character) revision history date (yy/mm/dd) revision reason page contents 05/08/10 00 first edition important notice ? these products and their specifications are subject to change without notice. before considering any use or application, consult the asahi kasei microsystems co., ltd. (akm) sales office or authorized distributor concerning their current status. ? akm assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. ? any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. ? akm products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, an d akm assumes no responsibility relating to any such use, except with the express written consent of the representative director of akm. as used here: a. a hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. b. a critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefor e meet very high standards of performance and reliability. ? it is the responsibility of the buyer or distributor of an akm product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold akm harmless from any and all claims arising from the use of said product in the absence of such notification.

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